This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-086385, filed Mar. 27, 2000; and No. 2000-325047, filed Oct. 25, 2000, the entire contents of both of which are incorporated herein by reference.
This invention relates to a level converter circuit operated by using a plurality of power supplies.
Recently, the number of semiconductor elements formed on a chip has significantly increased. Several hundreds of millions of semiconductor elements are integrated per chip in a gigabit-order semiconductor memory, and several tens of thousands to tens of millions of semiconductor elements are integrated per chip in a 64-bit microprocessor. The number of semiconductor elements formed on a chip can be improved by reducing the size of semiconductor elements. Currently, in a 1-Gbit DRAM (Dynamic Random Access Memory), MOS transistors with a gate length of 0.15 xcexcm are used. To further increase the number of semiconductor elements formed on a chip, MOS transistors with a gate length of 0.1 xcexcm or less will need to be used.
In the above fine patterned MOS transistor, hot carriers deteriorate the transistor and an insulating film is destroyed by TDDB (Time Dependent Dielectric Breakdown). Further, a junction breakdown voltage of a source and drain is lowered when the impurity concentrations of a substrate region and a channel region are increased in order to suppress a lowering in a threshold voltage due to a reduction in the channel length. Lowering a power supply voltage keeps the reliability of the fine patterned element high. That is, weakening a lateral electric field between the source and the drain prevents hot carriers and weakening the vertical electric field between the gate and the bulk prevents TDDB. Further, by lowering the power supply voltage, reverse bias voltages applied to a junction between the source and the bulk and a junction between the drain and the bulk are lowered so as to cope with a lowering in a withstand voltage.
Recently, the market for portable information devices has remarkably increased. Most of the portable information devices employ a lightweight power supply, such as a lithium ion battery having a high energy density. However, the three volts (3V) of the lithium ion battery is higher than the withstand voltage of the fine patterned MOS transistor. Therefore, when the lithium ion battery is applied to a circuit comprising the fine patterned transistor, a power supply voltage converter must be used to reduce the voltage. The power consumed during the operation of a CMOS circuit used in a logic circuit is not only proportional to an operational frequency, but also proportional to the square of the power supply voltage. Therefore, reducing the power supply voltage significantly lowers the power consumption in the chip.
Therefore, to use a portable device for a longer period of time, it is required to develop a battery with high energy density, a power supply conversion circuit with high efficiency, and an integrated circuit operated at a low voltage. It is desirable to use the lowered power supply voltage in a base-band LSI and microprocessor with large power consumption from the viewpoint of attainment of the low power consumption.
In the portable information device, it is necessary to use a memory device such as a DRAM or SRAM in addition to a logic circuit. The DRAM is designed to attain a sufficient charge amount of a cell to enhance a soft error resistance and the SRAM is designed to prevent a lowering in the operation speed at the time of the low-voltage operation. Therefore, there are no significant measures for making the power consumption low as in the logic circuit, and at present, elements operated on a power supply voltage of approximately 1.75V are put into practice. However, since the power supply voltage of the memory circuit is greatly different from that of the logic circuit, it is necessary to use a multiple power supply construction for supplying various power supply voltages in an LSI having a memory circuit and a logic circuit.
FIG. 1 shows the construction of a semiconductor integrated circuit 405 for a portable information device having a memory circuit and logic circuit integrated on one chip and a power supply system thereof. The circuit of FIG. 1 includes a lithium battery (lithium ion secondary battery) 400, a power supply conversion circuit 401, a logic circuit 402, an on-chip memory circuit 403, and a level converter 404. The output power supply voltage 3V of the lithium battery 400 is converted into 0.5V by the power supply conversion circuit 401 to supply a 0.5V power supply voltage to the logic circuit 402. Since the on-chip memory circuit 403 requires a power supply voltage of 1V or more for its operation, the output power supply voltage 3V of the lithium battery 400 is supplied directly to the memory circuit 403. The 3V power supply voltage and 0.5V power supply voltage are supplied to the level converter 404, which connects the memory circuit 403 and logic circuit 402.
With the construction shown in FIG. 1, setting the power supply voltage of the logic circuit 402 to 0.5V can lower the power consumption at an operation time. However, when the power supply voltage of a general CMOS circuit is simply lowered from 3V and operated on a power supply voltage of 2V, , the operation speed of the device is lowered or the device will not correctly operate. To solve the above problem, it is necessary to lower the threshold voltage of the MOS transistor with a lowering in the power supply voltage. For example, to construct a logic circuit that operates on a low power supply voltage of 0.5V, it is necessary to use an FET having a threshold voltage of 0.1V to 0.2V in the absolute value that is equal to approximately ⅓ of the threshold voltage of the conventional FET.
However, if the above threshold value is used, a leakage current of the FET at the OFF time is greatly increased, and as a result, the power consumption of the device at the standby time is greatly increased and the semiconductor integrated circuit for the portable information device cannot be suitably used as it is.
FIG. 2 shows the construction of a semiconductor integrated circuit and a power supply system thereof constructed by taking the above problem into consideration. In FIG. 2, four kinds of power supply voltages (VDD, VD1, VS1, VSS) including a ground potential are supplied to a semiconductor integrated circuit 506. A 3V power supply voltage (VDD) supplied from a lithium battery 500, a ground potential (VSS), and VD1 and VS1 supplied from a power supply conversion circuit 501 are supplied to a logic circuit 502 integrated on a chip in the semiconductor integrated circuit 506. In this case, a potential difference between the logic circuit power supply voltage VD1 and the logic circuit ground voltage VS1 is set at 0.5V.
With the above construction, the logic circuit 502 is operated by use of two voltages VD1 and VS1 to lower the power consumption at the operation time. Further, in the standby state, the well potential of a p-channel MOSFET 509 is set to VDD from VD1 by setting a p-channel MOSFET 507 to the ON state and the well potential of an n-channel MOSFET 510 is set to VSS from VS1 by setting an n-channel MOSFET 508 to the ON state. As a result, the absolute values of the threshold voltages of the MOSFETs 509 and 510 in the logic circuit at the standby time are increased and the leakage current at the OFF time thereof is reduced, thereby making it possible to lower the power consumption in the standby state.
As to the power supply for on-chip memory circuits 503, 504 and 505, the following three constructions are considered.
1) The chip power supply voltage VDD and chip ground potential VSS supplied from the lithium battery are used.
2) The logic circuit power supply voltage VD1 and chip ground potential VSS are used.
3) The chip power supply voltage VDD and logic circuit ground potential VS1 are used.
The construction 2) or 3) is better than the construction 1) from the viewpoint of power consumption, but the construction to be selected is finally determined by taking the range of the operation voltage of the memory circuit into consideration. In the semiconductor integrated circuit 506 of FIG. 2, the high level is VD1 and the low level is VS1 in the logic circuit 502, the high level is VDD and the low level is VSS in the memory circuit 503, the high level is VD1 and the low level is VSS in the level converter 504, the high level is VDD and the low level is VS1 in the memory circuit 505, and thus various logic swings and various logic levels are used.
FIG. 3 shows the construction of a semiconductor integrated circuit and a power supply system thereof constructed by taking a problem of a leakage current at the OFF time into consideration. In the circuit of FIG. 3, three kinds of power supply voltages are supplied to a semiconductor integrated circuit 605. That is, a power supply voltage (VDD) and ground potential (VSS) from a nickel-hydrogen secondary battery (1.2V) or lithium ion secondary battery 600 (3V) are supplied to a logic circuit 602 integrated on a chip in the semiconductor integrated circuit 605. A power supply voltage VDDV is supplied to a CMOS circuit in the logic circuit 602. The power supply voltage VDDV is obtained by passing the logic circuit power supply voltage VD1 (0.5V), which is supplied from the power supply conversion circuit 601, through a p-channel MOSFET 603 having a high threshold voltage
With the above construction, in the standby state, after necessary information in the logic circuit is saved into the memory circuit 604, the gate voltage of the p-channel MOSFET 603 is set to VDD to set the MOSFET 603 into the OFF state. At this time, the leakage current of the logic circuit 602 becomes extremely small because it is determined by the OFF characteristic of the p-channel MOSFET 603 having a high threshold voltage.
However, since it is difficult to operate the memory circuit 605 on the power supply voltage of approximately 0.5V, it is driven by use of VDD and VSS, and the high level VD1 and the low level VSS are provided in the logic circuit and the high level VDD and the low level VSS are provided in the memory circuit, and thus two kinds of logic levels are used.
As described above, a multiple power supply system is indispensable for a portable device LSI, and a level converter of low power consumption for converting the logic levels according to the different power supply voltages is required. To transfer a signal from the semiconductor integrated circuit in which the logic swing is large to the logic circuit in which the logic swing is small, it is possible to effect the level conversion without causing any problem by use of a normal CMOS circuit as shown in FIG. 4 which uses MOSFETs having a gate breakdown voltage VBD higher than the logic swing (VDDxe2x88x92VSS).
However, it is difficult to convert the signal level of a logic circuit with a logic swing (0.5V in this example) that is as small as (VD1xe2x88x92VS1) to a large logic swing for the memory circuit. For example, in a normal CMOS inverter circuit shown in FIG. 4, various problems will occur when the signal level is sufficiently converted to the logic level of the memory circuit, for example, (VDD, VSS), (VD1, VSS), (VDD, VS1). That is, 1) the complete level conversion cannot be attained by use of the one-stage CMOS inverter, 2) neither the p-channel MOSFET nor the n-channel MOSFET can be cut OFF by use of the one-stage CMOS inverter and it is operated in the ON state as in a Class xe2x80x9cAxe2x80x9d amplifier, and as a result, a stationary short circuit current flows from the power supply to the ground node, and 3) if a multi-stage CMOS inverter is used, the power consumption becomes large.
As another method, there is provided a method using a differential amplifier and using an intermediate value between VD1 and VS1 as a reference voltage. However, even in this method, the power consumption becomes large by the following reasons: 1) a power supply for the differential amplifier is required and 2) a CMOS inverter for amplifying an output of the differential amplifier is required and a consumption current in the CMOS inverter stage is added.
In order to cope with the above problem, a level converter for converting the logic swing of approximately 0.5V to 1V to the logic swing of approximately 2V is proposed (Sub-1-V Swing Bus Architecture for Future Low-Power ULSIs by Nakagome et. al., 1992 VLSI Circuit Symposium, 9-2). The level converter disclosed in the above document is shown in FIG. 5 and attains the low power consumption characteristics.
The level converter of FIG. 5 includes gate-grounded MOSFETs 800 and 801 and two cross-coupled FETs constituted of two MOSFETs of the same channel type in which the gate and source of one MOSFET are respectively connected to the source and gate of the other MOSFET. However, since the logic swings of the gate voltages input to the cross-coupled MOSFETs of the same channel type are greatly different from each other, the driving capabilities of the MOSFETs constructing the cross-coupled FETs are resultantly greatly different if the two MOSFETs of the same size are used and it becomes difficult to attain the inverting operation by the MOSFET having a lower driving ability. Therefore, for each of the cross-coupled FETs, it is necessary to determine the sizes of the MOSFETs by taking the driving capabilities thereof into consideration.
Another problem with the level converter of FIG. 5 is that the tolerable amount for the element characteristics o is small. That is, a strict limitation is imposed on the element characteristics of the p-channel MOSFET 800 and n-channel MOSFET 801, and in order to attain the desired level conversion, for example, a MOSFET having a threshold voltage of 0V to approximately 0.05V is required. Requirements that a FET have such a special threshold voltage makes the manufacturing process complicated and since the tolerable range of the threshold voltage is as narrow as 100 mV, strict process control is required. Therefore, finally, the cost of the semiconductor integrated circuit is increased.
FIG. 6 shows the simulation result of the characteristics of the level converter of FIG. 5. In this case VS1 and VSS are set to the same potential. As shown in FIG. 7, the simulation is carried out by use of a circuit in which inverters driven by power supply voltages VD1 and VS1 are cascade-connected in the preceding stage of a level converter 900 and buffer inverters driven by power supply voltages VDD and VSS are connected in the succeeding stage thereof. A delay time between a signal input to the preceding stage inverter to be subjected to the level conversion and a signal output from the succeeding-stage buffer inverter is derived. A capacitor of 1 pF is connected as a load to each buffer inverter. The delay time is derived by averaging a time (tr) from when an input signal IN rises from VS1 to (VD1+VS1)/2 until an output signal OUT is changed and rises from VSS to (VDD+VSS)/2 and a time (tf) from when the input signal IN falls from VD1 to (VD1+VS1)/2 until the output signal OUT is changed and falls from VDD to (VDD+VSS)/2 (refer to FIG. 8).
In FIG. 6, the distribution of delay times is shown in the unit of ns when the level converter of FIG. 5 is operated by changing the power supply voltages VDD and VD1. The power supply voltage VD1 is assigned on the column of FIG. 6 and the power supply voltage VDD is assigned on the row. Space portions in which the delay time is not described indicate that the level converter is not operated.
The level converter is operated even when VD1 is lowered to approximately 1.3V to 1.4V, but if VD1 becomes lower than 1.2V, it does not operate. It is considered that this is because a difference between the logic swings of the gate voltages input to the MOSFETs of the same channel type constructing the cross-coupled FETs becomes larger when VD1 becomes lower, and a difference between the driving abilities of the FETs also becomes larger so that the inverting operation by the FET having a lower driving ability will become difficult.
This invention has been made in view of the above problems and provides a semiconductor integrated circuit for realizing a level converter having large tolerance for the element characteristic and low power consumption.
In accordance with the present invention there is provided a level converter circuit comprising:
a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, wherein the first and second input signals are complementary;
a first output terminal for outputting a first output signal and a second output terminal for outputting a second output signal, wherein the first and second output signals are complementary and wherein the voltage swing of the first and second complementary input signals is smaller than the voltage swing of the first and second complementary output signals;
at least first and second charge transfer MISFETs connected to the first and second input terminals;
a differential amplifier having first internal input terminals and first internal output terminals wherein the first internal input terminals are connected to the at least first and second charge transfer MISFETS; and
an output buffer having second internal input terminals and second internal output terminals wherein the second internal input terminals are connected to the first internal output terminals and the second internal output terminals are connected to the first and second output terminals.
Also in accordance with the present invention there is provided a level converter circuit comprising:
a first input terminal to which a first logic signal having a first logic swing is input;
a second input terminal to which a second logic signal which is an inverted signal of the first logic signal is input;
a first charge transfer MISFET having a first gate and a first conduction path wherein a conduction of the first conduction path is controlled by the first gate and wherein an end of the first conduction path is connected to the first input terminal;
a second charge transfer MISFET having a second gate and a second conduction path wherein a conduction of the second conduction path is controlled by the second gate and wherein an end of the second conduction path is connected to the second input terminal;
an amplifier having a first internal input terminal, a second internal input terminal, a first output terminal and a second output terminal wherein the other end of the first conduction path of the first charge transfer MISFET is connected to the first internal input terminal the other end of the second conduction path of the second charge transfer MISFET is connected to the second internal input terminal, the first output terminal outputs a third logic signal having a second logic swing different from the first logic swing, and the second output terminal outputs a fourth logic signal which is an inverted signal of the third logic signal.